1. Field of the Invention
The present invention relates to integrated circuits and, in particular, to circuitry which provides fast read access of serial memories utilizing a random starting address.
2. Description of the Prior Art
U.K. Patent Application GB No. 2 183 374 A is directed to a sequential access memory which provides serial read access, the ability for simultaneous read and write of data, and eliminates the need for complex addressing and refresh circuitry by using the memory as one large shift register.
The memory device disclosed in the above-identified U.K. application includes individual FET memory cells arranged in a matrix with a common set of column bit lines driven by bit line transistors to prepare the cells for read or write. The rows of the matrix are selected by a pointer register, a shift register in which a defined bit condition circulates to select the rows sequentially. The data input is offered to all cells in the first column and the cell outputs and inputs are merged so that the whole device acts as a serial shift register. When a cell is selected for read-out, its neighbor is selected for write-in, the selection using the appropriate gate primed from the shift register. As a result of the merging of inputs and outputs, a bit read from one cell goes to the cell in the next adjacent column and one up from the cell in the signal column. Thus, the data progresses through the memory matrix to the output.
However, the above-described sequential access memory suffers from a number of major disadvantages. First, it does not provide random access capability. Second, the data pattern in the array is altered if the sequential read is terminated in midstream. Third, the memory cannot be used as a shift register of variable lengths. These disadvantages limit the use of this memory device to specific applications.
U.S. Pat. No. 4,422,160 issued to Watanabe on Dec. 20, 1983, discloses a memory device which features serial access in a page-mode type of operation for RAMs and semi-random access capability. Its data pattern is not altered if sequential read is terminated in mid-stream. Fewer pins are required since row and column address information is introduced through the same set of address terminals in synchronism with row address strobe and column address strobe signals, respectively.
As stated above, in the Watanabe memory device, row address information and column address information are incorporated through the same set of address terminals in response to a row address strobe signal and a column address strobe signal, respectively. Furthermore, a shift register, the output of which is adapted to select a column of a memory cell matrix, is provided in addition to a column decoder. The shift operation of the shift register is effected each time the column strobe signal is made active under the active state of the row address strobe signal. The significant feature of the Watanabe memory device resides in the fact that the column address decoder and the column address inverter are made their active states when the column address strobe signal is first made active under the active state of the row strobe signal; these states of the column address inverter and column decoder are maintained irrespective of subsequent change of the column address strobe signal by the time the row strobe signal goes inactive. The shift register and an input/output circuit are repeatedly made active in synchronism with changes in the level of the column strobe signals between its active and inactive states under the active state of the row address strobe signal. Thus, in the operation of the Watanabe device, the shift operation in the shift register and activation of the input/output circuit can be repeatedly performed at a high speed and with low power consumption without repeating the active and inactive state of the column address inverter buffer and the column decoder.
However, the Watanabe memory device also suffers from several disadvantages. First, it does not provide a fully random access capability because a new row address must be provided after all the columns along a particular row have been read out. Second, the Watanabe device cannot be used as a shift register of variable lengths. Therefore, like the device described in the above-identified UK application, the Watanabe memory device is also limited to use in specific applications.